These are widely accepted and used in the ceramic capacitor industry.

• Active area: refers to the total area of all left and right internal electrodes in the MLCC staggered and overlapped, and an effective ceramic medium is filled between the two staggered and overlapped internal electrodes.
• Active dielectric: The ceramic insulating medium between all interlaced and overlapping internal electrodes inside the MLCC ceramic body.
• Artifact: Any abnormality caused by the DPA analysis process that was not present in the sample prior to DPA processing. For example, stress relief cracks, surface cracks, and electrode displacement that may occur during polishing.
• Bandwidth (band width): MLCC two terminal electrode coating width dimension, from the end of the chip terminal electrode to cover the width of the ceramic body.

• Barrier layer (Barrier layer): The outermost layer of the MLCC terminal electrode is tin-plated, and the second plating layer inside is a nickel barrier layer, which protects the internal electrodes in the state of molten tin during soldering. Please refer to Section 4.3 NME and BME Process Schematic.
• Cold soldering (cold solder): Bad solder joints caused by incomplete reflow soldering, weak diversion or sporadic infiltration during the soldering process. From the surface, it is characterized by dull, granular and porous surfaces. From the inside, Cold soldering is characterized by excessive pinholes and possible residual flux.
• Capacitor element: A ceramic chip body with terminal electrode plating.
• Ceramic body (Chip element): For DPA analysis, the ceramic body removes the end electrode plating and only contains the inner electrode.
• Crack: A crack or separation that occurs inside the MLCC. Cracks may be caused by improper manufacturing processes or materials, or induced by DPA processing or environmental stress.
• Delamination: Separation between two layers of ceramic dielectric, or between a ceramic laminate and the interface of an internal electrode, or, less commonly, within a single layer of ceramic approximately parallel to the plane of the internal electrode.
• Destructive Physical Analysis (DPA): Sectional analysis performed to examine the internal characteristics of an object or device, which results in partial or total destruction of the object being analyzed. For chip ceramic capacitors, this may include etching, grinding, polishing and microscopic examination. In some cases, it may also include resistance to soldering thermal shock (RSH), visual inspection prior to DPA, and electrical testing.
• Dielectric: Dielectric ceramic between interleaved and overlapping internal electrodes.
• Media voids: Vacuum voids or agglomeration of several voids within a layer of media, even through a layer in some cases.
• Leaching: Due to the action of molten solder, the end metal of the chip capacitor is eroded, and the end plating melted into tin melt.
• Microcrack: A very fine crack in a ceramic that is only visible with indirect, darkfield, or polarized light at relatively high magnifications (typically above 1x). Actual microcracks occur as a result of stresses within the ceramic body or the release of such forces.
• Overlap view: A longitudinal section view of a chip capacitor showing staggered overlapping inner electrode edges, terminal the side line, the terminal electrode plating layer, and the ceramic body and solder joints, the section is perpendicular to the internal electrode layer and the ceramic layer.